// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
// Date        : Tue Nov 26 18:05:59 2019
// Host        : ubuntu running 64-bit Ubuntu 18.04.3 LTS
// Command     : write_verilog -mode timesim -nolib -sdf_anno true -force -file
//               /home/cyx/Desktop/WEEK12-EDA-Laboratory-of-Electronic-Circuits/Module_1/M1.sim/sim_1/impl/timing/xsim/counter_test_tb_time_impl.v
// Design      : counter_test
// Purpose     : This verilog netlist is a timing simulation representation of the design and should not be modified or
//               synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING

(* ECO_CHECKSUM = "400514a5" *) (* MAX = "3'b101" *) 
(* NotValidForBitStream *)
module counter_test
   (CLK,
    RST,
    CNT);
  input CLK;
  input RST;
  output [3:0]CNT;

  wire CLK;
  wire CLK_IBUF;
  wire CLK_IBUF_BUFG;
  wire [3:0]CNT;
  wire \CNT[0]_i_1_n_0 ;
  wire \CNT[1]_i_1_n_0 ;
  wire \CNT[2]_i_1_n_0 ;
  wire \CNT[3]_i_1_n_0 ;
  wire [3:0]CNT_OBUF;
  wire RST;
  wire RST_IBUF;

initial begin
 $sdf_annotate("counter_test_tb_time_impl.sdf",,,,"tool_control");
end
  BUFG CLK_IBUF_BUFG_inst
       (.I(CLK_IBUF),
        .O(CLK_IBUF_BUFG));
  IBUF CLK_IBUF_inst
       (.I(CLK),
        .O(CLK_IBUF));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \CNT[0]_i_1 
       (.I0(CNT_OBUF[0]),
        .O(\CNT[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'h0FB0)) 
    \CNT[1]_i_1 
       (.I0(CNT_OBUF[3]),
        .I1(CNT_OBUF[2]),
        .I2(CNT_OBUF[0]),
        .I3(CNT_OBUF[1]),
        .O(\CNT[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'h3C8C)) 
    \CNT[2]_i_1 
       (.I0(CNT_OBUF[3]),
        .I1(CNT_OBUF[2]),
        .I2(CNT_OBUF[0]),
        .I3(CNT_OBUF[1]),
        .O(\CNT[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \CNT[3]_i_1 
       (.I0(CNT_OBUF[3]),
        .I1(CNT_OBUF[2]),
        .I2(CNT_OBUF[0]),
        .I3(CNT_OBUF[1]),
        .O(\CNT[3]_i_1_n_0 ));
  OBUF \CNT_OBUF[0]_inst 
       (.I(CNT_OBUF[0]),
        .O(CNT[0]));
  OBUF \CNT_OBUF[1]_inst 
       (.I(CNT_OBUF[1]),
        .O(CNT[1]));
  OBUF \CNT_OBUF[2]_inst 
       (.I(CNT_OBUF[2]),
        .O(CNT[2]));
  OBUF \CNT_OBUF[3]_inst 
       (.I(CNT_OBUF[3]),
        .O(CNT[3]));
  FDCE #(
    .INIT(1'b0)) 
    \CNT_reg[0] 
       (.C(CLK_IBUF_BUFG),
        .CE(1'b1),
        .CLR(RST_IBUF),
        .D(\CNT[0]_i_1_n_0 ),
        .Q(CNT_OBUF[0]));
  FDCE #(
    .INIT(1'b0)) 
    \CNT_reg[1] 
       (.C(CLK_IBUF_BUFG),
        .CE(1'b1),
        .CLR(RST_IBUF),
        .D(\CNT[1]_i_1_n_0 ),
        .Q(CNT_OBUF[1]));
  FDCE #(
    .INIT(1'b0)) 
    \CNT_reg[2] 
       (.C(CLK_IBUF_BUFG),
        .CE(1'b1),
        .CLR(RST_IBUF),
        .D(\CNT[2]_i_1_n_0 ),
        .Q(CNT_OBUF[2]));
  FDCE #(
    .INIT(1'b0)) 
    \CNT_reg[3] 
       (.C(CLK_IBUF_BUFG),
        .CE(1'b1),
        .CLR(RST_IBUF),
        .D(\CNT[3]_i_1_n_0 ),
        .Q(CNT_OBUF[3]));
  IBUF RST_IBUF_inst
       (.I(RST),
        .O(RST_IBUF));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
